require '_h2ph_pre.ph';

unless(defined(&_SYNCLINK_H_)) {
    eval 'sub _SYNCLINK_H_ () {1;}' unless defined(&_SYNCLINK_H_);
    eval 'sub SYNCLINK_H_VERSION () {3.5;}' unless defined(&SYNCLINK_H_VERSION);
    eval 'sub BOOLEAN () {\'int\';}' unless defined(&BOOLEAN);
    eval 'sub TRUE () {1;}' unless defined(&TRUE);
    eval 'sub FALSE () {0;}' unless defined(&FALSE);
    eval 'sub BIT0 () {0x1;}' unless defined(&BIT0);
    eval 'sub BIT1 () {0x2;}' unless defined(&BIT1);
    eval 'sub BIT2 () {0x4;}' unless defined(&BIT2);
    eval 'sub BIT3 () {0x8;}' unless defined(&BIT3);
    eval 'sub BIT4 () {0x10;}' unless defined(&BIT4);
    eval 'sub BIT5 () {0x20;}' unless defined(&BIT5);
    eval 'sub BIT6 () {0x40;}' unless defined(&BIT6);
    eval 'sub BIT7 () {0x80;}' unless defined(&BIT7);
    eval 'sub BIT8 () {0x100;}' unless defined(&BIT8);
    eval 'sub BIT9 () {0x200;}' unless defined(&BIT9);
    eval 'sub BIT10 () {0x400;}' unless defined(&BIT10);
    eval 'sub BIT11 () {0x800;}' unless defined(&BIT11);
    eval 'sub BIT12 () {0x1000;}' unless defined(&BIT12);
    eval 'sub BIT13 () {0x2000;}' unless defined(&BIT13);
    eval 'sub BIT14 () {0x4000;}' unless defined(&BIT14);
    eval 'sub BIT15 () {0x8000;}' unless defined(&BIT15);
    eval 'sub BIT16 () {0x10000;}' unless defined(&BIT16);
    eval 'sub BIT17 () {0x20000;}' unless defined(&BIT17);
    eval 'sub BIT18 () {0x40000;}' unless defined(&BIT18);
    eval 'sub BIT19 () {0x80000;}' unless defined(&BIT19);
    eval 'sub BIT20 () {0x100000;}' unless defined(&BIT20);
    eval 'sub BIT21 () {0x200000;}' unless defined(&BIT21);
    eval 'sub BIT22 () {0x400000;}' unless defined(&BIT22);
    eval 'sub BIT23 () {0x800000;}' unless defined(&BIT23);
    eval 'sub BIT24 () {0x1000000;}' unless defined(&BIT24);
    eval 'sub BIT25 () {0x2000000;}' unless defined(&BIT25);
    eval 'sub BIT26 () {0x4000000;}' unless defined(&BIT26);
    eval 'sub BIT27 () {0x8000000;}' unless defined(&BIT27);
    eval 'sub BIT28 () {0x10000000;}' unless defined(&BIT28);
    eval 'sub BIT29 () {0x20000000;}' unless defined(&BIT29);
    eval 'sub BIT30 () {0x40000000;}' unless defined(&BIT30);
    eval 'sub BIT31 () {0x80000000;}' unless defined(&BIT31);
    eval 'sub HDLC_MAX_FRAME_SIZE () {65535;}' unless defined(&HDLC_MAX_FRAME_SIZE);
    eval 'sub MAX_ASYNC_TRANSMIT () {4096;}' unless defined(&MAX_ASYNC_TRANSMIT);
    eval 'sub MAX_ASYNC_BUFFER_SIZE () {4096;}' unless defined(&MAX_ASYNC_BUFFER_SIZE);
    eval 'sub ASYNC_PARITY_NONE () {0;}' unless defined(&ASYNC_PARITY_NONE);
    eval 'sub ASYNC_PARITY_EVEN () {1;}' unless defined(&ASYNC_PARITY_EVEN);
    eval 'sub ASYNC_PARITY_ODD () {2;}' unless defined(&ASYNC_PARITY_ODD);
    eval 'sub ASYNC_PARITY_SPACE () {3;}' unless defined(&ASYNC_PARITY_SPACE);
    eval 'sub HDLC_FLAG_UNDERRUN_ABORT7 () {0x;}' unless defined(&HDLC_FLAG_UNDERRUN_ABORT7);
    eval 'sub HDLC_FLAG_UNDERRUN_ABORT15 () {0x1;}' unless defined(&HDLC_FLAG_UNDERRUN_ABORT15);
    eval 'sub HDLC_FLAG_UNDERRUN_FLAG () {0x2;}' unless defined(&HDLC_FLAG_UNDERRUN_FLAG);
    eval 'sub HDLC_FLAG_UNDERRUN_CRC () {0x4;}' unless defined(&HDLC_FLAG_UNDERRUN_CRC);
    eval 'sub HDLC_FLAG_SHARE_ZERO () {0x10;}' unless defined(&HDLC_FLAG_SHARE_ZERO);
    eval 'sub HDLC_FLAG_AUTO_CTS () {0x20;}' unless defined(&HDLC_FLAG_AUTO_CTS);
    eval 'sub HDLC_FLAG_AUTO_DCD () {0x40;}' unless defined(&HDLC_FLAG_AUTO_DCD);
    eval 'sub HDLC_FLAG_AUTO_RTS () {0x80;}' unless defined(&HDLC_FLAG_AUTO_RTS);
    eval 'sub HDLC_FLAG_RXC_DPLL () {0x100;}' unless defined(&HDLC_FLAG_RXC_DPLL);
    eval 'sub HDLC_FLAG_RXC_BRG () {0x200;}' unless defined(&HDLC_FLAG_RXC_BRG);
    eval 'sub HDLC_FLAG_RXC_TXCPIN () {0x8000;}' unless defined(&HDLC_FLAG_RXC_TXCPIN);
    eval 'sub HDLC_FLAG_RXC_RXCPIN () {0x;}' unless defined(&HDLC_FLAG_RXC_RXCPIN);
    eval 'sub HDLC_FLAG_TXC_DPLL () {0x400;}' unless defined(&HDLC_FLAG_TXC_DPLL);
    eval 'sub HDLC_FLAG_TXC_BRG () {0x800;}' unless defined(&HDLC_FLAG_TXC_BRG);
    eval 'sub HDLC_FLAG_TXC_TXCPIN () {0x;}' unless defined(&HDLC_FLAG_TXC_TXCPIN);
    eval 'sub HDLC_FLAG_TXC_RXCPIN () {0x8;}' unless defined(&HDLC_FLAG_TXC_RXCPIN);
    eval 'sub HDLC_FLAG_DPLL_DIV8 () {0x1000;}' unless defined(&HDLC_FLAG_DPLL_DIV8);
    eval 'sub HDLC_FLAG_DPLL_DIV16 () {0x2000;}' unless defined(&HDLC_FLAG_DPLL_DIV16);
    eval 'sub HDLC_FLAG_DPLL_DIV32 () {0x;}' unless defined(&HDLC_FLAG_DPLL_DIV32);
    eval 'sub HDLC_FLAG_HDLC_LOOPMODE () {0x4000;}' unless defined(&HDLC_FLAG_HDLC_LOOPMODE);
    eval 'sub HDLC_CRC_NONE () {0;}' unless defined(&HDLC_CRC_NONE);
    eval 'sub HDLC_CRC_16_CCITT () {1;}' unless defined(&HDLC_CRC_16_CCITT);
    eval 'sub HDLC_CRC_32_CCITT () {2;}' unless defined(&HDLC_CRC_32_CCITT);
    eval 'sub HDLC_CRC_MASK () {0xff;}' unless defined(&HDLC_CRC_MASK);
    eval 'sub HDLC_CRC_RETURN_EX () {0x8000;}' unless defined(&HDLC_CRC_RETURN_EX);
    eval 'sub RX_OK () {0;}' unless defined(&RX_OK);
    eval 'sub RX_CRC_ERROR () {1;}' unless defined(&RX_CRC_ERROR);
    eval 'sub HDLC_TXIDLE_FLAGS () {0;}' unless defined(&HDLC_TXIDLE_FLAGS);
    eval 'sub HDLC_TXIDLE_ALT_ZEROS_ONES () {1;}' unless defined(&HDLC_TXIDLE_ALT_ZEROS_ONES);
    eval 'sub HDLC_TXIDLE_ZEROS () {2;}' unless defined(&HDLC_TXIDLE_ZEROS);
    eval 'sub HDLC_TXIDLE_ONES () {3;}' unless defined(&HDLC_TXIDLE_ONES);
    eval 'sub HDLC_TXIDLE_ALT_MARK_SPACE () {4;}' unless defined(&HDLC_TXIDLE_ALT_MARK_SPACE);
    eval 'sub HDLC_TXIDLE_SPACE () {5;}' unless defined(&HDLC_TXIDLE_SPACE);
    eval 'sub HDLC_TXIDLE_MARK () {6;}' unless defined(&HDLC_TXIDLE_MARK);
    eval 'sub HDLC_ENCODING_NRZ () {0;}' unless defined(&HDLC_ENCODING_NRZ);
    eval 'sub HDLC_ENCODING_NRZB () {1;}' unless defined(&HDLC_ENCODING_NRZB);
    eval 'sub HDLC_ENCODING_NRZI_MARK () {2;}' unless defined(&HDLC_ENCODING_NRZI_MARK);
    eval 'sub HDLC_ENCODING_NRZI_SPACE () {3;}' unless defined(&HDLC_ENCODING_NRZI_SPACE);
    eval 'sub HDLC_ENCODING_NRZI () { &HDLC_ENCODING_NRZI_SPACE;}' unless defined(&HDLC_ENCODING_NRZI);
    eval 'sub HDLC_ENCODING_BIPHASE_MARK () {4;}' unless defined(&HDLC_ENCODING_BIPHASE_MARK);
    eval 'sub HDLC_ENCODING_BIPHASE_SPACE () {5;}' unless defined(&HDLC_ENCODING_BIPHASE_SPACE);
    eval 'sub HDLC_ENCODING_BIPHASE_LEVEL () {6;}' unless defined(&HDLC_ENCODING_BIPHASE_LEVEL);
    eval 'sub HDLC_ENCODING_DIFF_BIPHASE_LEVEL () {7;}' unless defined(&HDLC_ENCODING_DIFF_BIPHASE_LEVEL);
    eval 'sub HDLC_PREAMBLE_LENGTH_8BITS () {0;}' unless defined(&HDLC_PREAMBLE_LENGTH_8BITS);
    eval 'sub HDLC_PREAMBLE_LENGTH_16BITS () {1;}' unless defined(&HDLC_PREAMBLE_LENGTH_16BITS);
    eval 'sub HDLC_PREAMBLE_LENGTH_32BITS () {2;}' unless defined(&HDLC_PREAMBLE_LENGTH_32BITS);
    eval 'sub HDLC_PREAMBLE_LENGTH_64BITS () {3;}' unless defined(&HDLC_PREAMBLE_LENGTH_64BITS);
    eval 'sub HDLC_PREAMBLE_PATTERN_NONE () {0;}' unless defined(&HDLC_PREAMBLE_PATTERN_NONE);
    eval 'sub HDLC_PREAMBLE_PATTERN_ZEROS () {1;}' unless defined(&HDLC_PREAMBLE_PATTERN_ZEROS);
    eval 'sub HDLC_PREAMBLE_PATTERN_FLAGS () {2;}' unless defined(&HDLC_PREAMBLE_PATTERN_FLAGS);
    eval 'sub HDLC_PREAMBLE_PATTERN_10 () {3;}' unless defined(&HDLC_PREAMBLE_PATTERN_10);
    eval 'sub HDLC_PREAMBLE_PATTERN_01 () {4;}' unless defined(&HDLC_PREAMBLE_PATTERN_01);
    eval 'sub HDLC_PREAMBLE_PATTERN_ONES () {5;}' unless defined(&HDLC_PREAMBLE_PATTERN_ONES);
    eval 'sub MGSL_MODE_ASYNC () {1;}' unless defined(&MGSL_MODE_ASYNC);
    eval 'sub MGSL_MODE_HDLC () {2;}' unless defined(&MGSL_MODE_HDLC);
    eval 'sub MGSL_MODE_RAW () {6;}' unless defined(&MGSL_MODE_RAW);
    eval 'sub MGSL_BUS_TYPE_ISA () {1;}' unless defined(&MGSL_BUS_TYPE_ISA);
    eval 'sub MGSL_BUS_TYPE_EISA () {2;}' unless defined(&MGSL_BUS_TYPE_EISA);
    eval 'sub MGSL_BUS_TYPE_PCI () {5;}' unless defined(&MGSL_BUS_TYPE_PCI);
    eval 'sub MICROGATE_VENDOR_ID () {0x13c0;}' unless defined(&MICROGATE_VENDOR_ID);
    eval 'sub SYNCLINK_DEVICE_ID () {0x10;}' unless defined(&SYNCLINK_DEVICE_ID);
    eval 'sub MGSCC_DEVICE_ID () {0x20;}' unless defined(&MGSCC_DEVICE_ID);
    eval 'sub SYNCLINK_SCA_DEVICE_ID () {0x30;}' unless defined(&SYNCLINK_SCA_DEVICE_ID);
    eval 'sub MGSL_MAX_SERIAL_NUMBER () {30;}' unless defined(&MGSL_MAX_SERIAL_NUMBER);
    eval 'sub DiagStatus_OK () {0;}' unless defined(&DiagStatus_OK);
    eval 'sub DiagStatus_AddressFailure () {1;}' unless defined(&DiagStatus_AddressFailure);
    eval 'sub DiagStatus_AddressConflict () {2;}' unless defined(&DiagStatus_AddressConflict);
    eval 'sub DiagStatus_IrqFailure () {3;}' unless defined(&DiagStatus_IrqFailure);
    eval 'sub DiagStatus_IrqConflict () {4;}' unless defined(&DiagStatus_IrqConflict);
    eval 'sub DiagStatus_DmaFailure () {5;}' unless defined(&DiagStatus_DmaFailure);
    eval 'sub DiagStatus_DmaConflict () {6;}' unless defined(&DiagStatus_DmaConflict);
    eval 'sub DiagStatus_PciAdapterNotFound () {7;}' unless defined(&DiagStatus_PciAdapterNotFound);
    eval 'sub DiagStatus_CantAssignPciResources () {8;}' unless defined(&DiagStatus_CantAssignPciResources);
    eval 'sub DiagStatus_CantAssignPciMemAddr () {9;}' unless defined(&DiagStatus_CantAssignPciMemAddr);
    eval 'sub DiagStatus_CantAssignPciIoAddr () {10;}' unless defined(&DiagStatus_CantAssignPciIoAddr);
    eval 'sub DiagStatus_CantAssignPciIrq () {11;}' unless defined(&DiagStatus_CantAssignPciIrq);
    eval 'sub DiagStatus_MemoryError () {12;}' unless defined(&DiagStatus_MemoryError);
    eval 'sub SerialSignal_DCD () {0x1;}' unless defined(&SerialSignal_DCD);
    eval 'sub SerialSignal_TXD () {0x2;}' unless defined(&SerialSignal_TXD);
    eval 'sub SerialSignal_RI () {0x4;}' unless defined(&SerialSignal_RI);
    eval 'sub SerialSignal_RXD () {0x8;}' unless defined(&SerialSignal_RXD);
    eval 'sub SerialSignal_CTS () {0x10;}' unless defined(&SerialSignal_CTS);
    eval 'sub SerialSignal_RTS () {0x20;}' unless defined(&SerialSignal_RTS);
    eval 'sub SerialSignal_DSR () {0x40;}' unless defined(&SerialSignal_DSR);
    eval 'sub SerialSignal_DTR () {0x80;}' unless defined(&SerialSignal_DTR);
    eval 'sub DEBUG_LEVEL_DATA () {1;}' unless defined(&DEBUG_LEVEL_DATA);
    eval 'sub DEBUG_LEVEL_ERROR () {2;}' unless defined(&DEBUG_LEVEL_ERROR);
    eval 'sub DEBUG_LEVEL_INFO () {3;}' unless defined(&DEBUG_LEVEL_INFO);
    eval 'sub DEBUG_LEVEL_BH () {4;}' unless defined(&DEBUG_LEVEL_BH);
    eval 'sub DEBUG_LEVEL_ISR () {5;}' unless defined(&DEBUG_LEVEL_ISR);
    eval 'sub MgslEvent_DsrActive () {0x1;}' unless defined(&MgslEvent_DsrActive);
    eval 'sub MgslEvent_DsrInactive () {0x2;}' unless defined(&MgslEvent_DsrInactive);
    eval 'sub MgslEvent_Dsr () {0x3;}' unless defined(&MgslEvent_Dsr);
    eval 'sub MgslEvent_CtsActive () {0x4;}' unless defined(&MgslEvent_CtsActive);
    eval 'sub MgslEvent_CtsInactive () {0x8;}' unless defined(&MgslEvent_CtsInactive);
    eval 'sub MgslEvent_Cts () {0xc;}' unless defined(&MgslEvent_Cts);
    eval 'sub MgslEvent_DcdActive () {0x10;}' unless defined(&MgslEvent_DcdActive);
    eval 'sub MgslEvent_DcdInactive () {0x20;}' unless defined(&MgslEvent_DcdInactive);
    eval 'sub MgslEvent_Dcd () {0x30;}' unless defined(&MgslEvent_Dcd);
    eval 'sub MgslEvent_RiActive () {0x40;}' unless defined(&MgslEvent_RiActive);
    eval 'sub MgslEvent_RiInactive () {0x80;}' unless defined(&MgslEvent_RiInactive);
    eval 'sub MgslEvent_Ri () {0xc0;}' unless defined(&MgslEvent_Ri);
    eval 'sub MgslEvent_ExitHuntMode () {0x100;}' unless defined(&MgslEvent_ExitHuntMode);
    eval 'sub MgslEvent_IdleReceived () {0x200;}' unless defined(&MgslEvent_IdleReceived);
    eval 'sub MGSL_MAGIC_IOC () {ord(\'m\');}' unless defined(&MGSL_MAGIC_IOC);
    eval 'sub MGSL_IOCSPARAMS () { &_IOW( &MGSL_MAGIC_IOC,0,\'struct _MGSL_PARAMS\');}' unless defined(&MGSL_IOCSPARAMS);
    eval 'sub MGSL_IOCGPARAMS () { &_IOR( &MGSL_MAGIC_IOC,1,\'struct _MGSL_PARAMS\');}' unless defined(&MGSL_IOCGPARAMS);
    eval 'sub MGSL_IOCSTXIDLE () { &_IO( &MGSL_MAGIC_IOC,2);}' unless defined(&MGSL_IOCSTXIDLE);
    eval 'sub MGSL_IOCGTXIDLE () { &_IO( &MGSL_MAGIC_IOC,3);}' unless defined(&MGSL_IOCGTXIDLE);
    eval 'sub MGSL_IOCTXENABLE () { &_IO( &MGSL_MAGIC_IOC,4);}' unless defined(&MGSL_IOCTXENABLE);
    eval 'sub MGSL_IOCRXENABLE () { &_IO( &MGSL_MAGIC_IOC,5);}' unless defined(&MGSL_IOCRXENABLE);
    eval 'sub MGSL_IOCTXABORT () { &_IO( &MGSL_MAGIC_IOC,6);}' unless defined(&MGSL_IOCTXABORT);
    eval 'sub MGSL_IOCGSTATS () { &_IO( &MGSL_MAGIC_IOC,7);}' unless defined(&MGSL_IOCGSTATS);
    eval 'sub MGSL_IOCWAITEVENT () { &_IOWR( &MGSL_MAGIC_IOC,8,\'int\');}' unless defined(&MGSL_IOCWAITEVENT);
    eval 'sub MGSL_IOCCLRMODCOUNT () { &_IO( &MGSL_MAGIC_IOC,15);}' unless defined(&MGSL_IOCCLRMODCOUNT);
    eval 'sub MGSL_IOCLOOPTXDONE () { &_IO( &MGSL_MAGIC_IOC,9);}' unless defined(&MGSL_IOCLOOPTXDONE);
}
1;
